The present invention relates to a driver for switching on and off stacked transistor circuits, and in particular, relates to the non-overlap time between the signals for the top transistor circuit and the bottom transistor circuit.
Design of a push-pull or totem pole driver on a switch mode power supply must ensure that both output devices are not switched on at the same time as this may lead to the destruction of either or both output transistor circuit devices. In order to achieve this, a cross-conduction circuit is built into the control chip. A cross-conduction prevention circuit is shown in FIG. 1. This circuit is designed to prevent both output devices MP1 and MN1 from being on at the same time. An input signal is sent to a NAND gate G2 and a NOR gate G1. The output from the NAND gate G2 is fed back to an input to the NOR gate G1. The output from the NOR gate G1 is fed to an input to the NAND gate G2. Inverters G3, G4 follow each of the logic gates providing additional delay in their respective circuit paths. In operation, when the input signal goes high for example, MP1 will be shut off before the high signal through the feedback path to the NAND gate G2 is able to turn on the bottom output device of MN1. While this circuit prevents cross-conduction, the inventor has recognized that the non-overlap time between the staggered outputs to the top and bottom outputs is a critical design tradeoff. If the non-overlap time is too small, the output devices can self-destruct. If the non-overlap time is too large, power supply efficiency is compromised.
In accordance with an embodiment of the method of the present invention, non-overlap time can be set for a staggered dual output driver to a desired value. A staggered dual output driver as used herein is one that provides drive signals to top and bottom outputs and encompasses push-pull drivers and totem pole drivers. Integrated circuits are provided with a plurality of delay paths for selective insertion in a feedback path between a first output and a logic gate for generating a second output. For each of the selectively inserted delay paths, the non-overlap time is detected. The integrated circuit is then set so as to use one of the tested delay paths. In a preferred embodiment, the integrated circuit has a plurality of paired delay paths, each pair of delay paths having one delay path for insertion in a first feedback path between a first output and a second logic gate for generating the second output and a second delay path for insertion in a second feedback path between the second output and a first logic gate for generating the first output. The delay paths are tested in pairs. After testing, one of the delay path pairs is selected for use in the integrated circuit. In a preferred embodiment, an encoder produces signals that select from among the delay paths. A signal sent to the encoder can permanently select one of the delay paths or delay path pairs.
The staggered dual output circuit of an embodiment of the invention includes a first logic circuit that generates a first output and a second logic circuit that generates a second output. Each of the logic circuits has a feedback path leading from its output to the other logic circuit. An encoder is included on the circuit permitting selection of any of a plurality of delay paths for insertion into one or both of the feedback paths. In a preferred embodiment, a pair of delay paths for insertion into each of the first and second feedback paths is selected.
In accordance with a further aspect of the invention, a staggered dual output driver includes a cross-conduction prevention circuit that provides a first output signal to a first feedback path and a second output signal to a second feedback path. A plurality of delay paths is provided for selective insertion into one or both of the feedback paths.
In accordance with a still further aspect of the invention, a first plurality of delay paths and a second plurality of delay paths emanate from a logic circuit. The integrated circuit includes a circuit for converting an input into a pair of successive signals. A selection input to the logic circuit is used to determine which of the delay paths will conduct between the pair of successive signals and top and bottom outputs.
Various embodiments of the invention permit the production of totem pole and push-pull drivers with accurately set non-overlap times. Other objects and advantages of the invention will become apparent during the following description of the presently preferred embodiments of the invention taken in conjunction with the drawings.